Integrated circuits such as processors, memory devices, memory controllers, input/output (I/O) controllers, and the like typically communicate with each other using digital data signals and clock signals. Some systems rely on clock signals having 50% duty cycles. When the duty cycle of these clock signals deviates much from 50%, circuits within the system may not operate as intended. Further, some systems rely on multiple clock signals having defined phase relationships. When the phase relationships deviate from the defined relationships, circuits within the system may not operate as intended. Some prior art integrated circuits include duty cycle detection circuits to detect whether a clock signal has a 50% duty cycle. Information from the duty cycle detection circuits can be utilized in a feedback loop to correct the duty cycle of the clock signal.
FIG. 1 shows a prior art duty cycle detection circuit. Circuit 100 receives a differential clock signal (CLK, CLK), and capacitors 102 and 104 operate as integrators to detect a duty cycle difference between CLK and CLK. The charge stored on capacitor 102 and capacitor 104 is a function of the duty cycle of the differential clock signal (CLK, CLK). Circuit 100 develops a differential voltage on nodes 106 and 108, and that differential voltage is an indication of the amount of duty cycle error in the differential clock signal.
In the example circuit 100, capacitors 102 and 104 operate as integrators to detect the duty cycle error, and also operate as charged storage devices to hold the duty cycle error information. If power is removed from circuit 100, the duty cycle error information on capacitors 102 and 104 may be lost, and a finite amount of time may be necessary upon the reapplication of power to reach a steady state duty cycle error value. Further discussion of circuit 100 may be found in “T. H. Lee et al., A 2.5V CMOS DLL for an 18 Mb 500 Mbps DRAM, JSSC, V.29 No. 12, 12/1994.”
In addition to analog duty cycle detection circuits such as circuit 100, digital duty cycle detection circuits exist. Rather than integrate duty cycle errors on analog capacitors, digital duty cycle detectors typically latch the values of clock signals at various times, make comparisons, and provide an indication of duty cycle error. Digital implementations typically suffer from a lack of precision due in part to the finite delay granularity of delay lines and set-up and hold requirements of digital storage elements. One digital duty cycle detection circuit is described in “C. Yoo et al., Open-Loop Full-Digital Duty Cycle Correction Circuit, Elec Ltrs, V.41 No. 11 5/2005.”